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LT5506 40MHz to 500MHz Quadrature Demodulator with VGA DESCRIPTIO
The LT(R)5506 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA), designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature down-converting mixers and lowpass noise filters. The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF down-conversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linearin-dB relationship to the control input voltage. Hard-clipping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The cut-off frequency of the noise filters is approximately 8.8MHz. The external 2xLO frequency is required to be twice the IF input frequency for the mixers. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s s s s
s s s s s s s s s s
Wide Range 1.8V to 5.25V Supply Frequency Range: 40MHz to 500MHz -4dB to 59dB Variable Power Gain THD < 0.12% (-58dBc) at 800mVP-P Differential Output Level 8.8MHz I/Q Lowpass Output Noise Filters IF Overload Detector Baseband I/Q Amplitude Imbalance: 0.2dB Baseband I/Q Phase Imbalance: 0.6 6.8dB Noise Figure at Max Gain Input IP3 at Low Gain: - 0.5dBm Low Supply Current: 27mA Low Delay Shift Over Gain Control Range: 2ps/dB Outputs Biased Up While in Standby 16-Lead QFN 4mm x 4mm Package with Exposed Pad
APPLICATIO S
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IEEE802.11 High Speed Wireless LAN Wireless Local Loop
TYPICAL APPLICATIO
280MHz IF INPUT L1 15nH C3 10pF L2 15nH
IF +
C2 1F
C1 1nF VCC
1.8V
-30 -35
IOUT+ IOUT-
THD (dBc)
IF -
-40 -45 -50 -55 -60 -60
GAIN CONTROL 2xLO C4 560MHz 3.3pF INPUT
VCTRL 2xLO + L3 39nH 2xLO - EN STBY GND /2
IF DET QOUT+ QOUT- LT5506
5506 TA01
C3 1.8pF
C5 3.3pF
ENABLE STANDBY
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Total Harmonic Distortion vs IF Input Level at 1.8V Supply
fIF, 1 = 280MHz fIF, 2 = 280.1MHz f2xLO = 570MHz 800mVP-P DIFFERENTIAL OUT
-40 -30 -20 -50 IF INPUT POWER EACH TONE (dBm)
-10
5506 TA01b
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ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Supply Voltage ....................................................... 5.5V Differential Voltage Between 2xLO+ and 2xLO- .......... 4V IF+, IF- ............................................. -500mV to 500mV IOUT+, IOUT-, QOUT+, QOUT- .................. VCC - 1.8V to VCC Operating Ambient Temperature (Note 2) ...................................................-40C to 85C Storage Temperature Range ..................-65C to 125C Voltage on Any Pin Not to Exceed ........................ -500mV to VCC + 500mV
QOUT+
16 15 14 13 GND 1 IF+ 2 IF - 3 GND 4 5 6 7 8 12 STBY 11 2xLO+ 10 2xLO- 9 EN
QOUT-
IOUT+
IOUT-
ORDER PART NUMBER LT5506EUF
IF DET
VCC
UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN
TJMAX = 125C, JA = 37C/W EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PRINTED CIRCUIT BOARD)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
VCC = 3V. f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
SYMBOL IF Input fIF Frequency Range Nominal Input Level Input Impedance NF GL GH IIP3 IIP2 Noise Figure at Max Gain Min Gain (Note 4) Max Gain (Note 4) Input IP3, Min Gain Input IP3, Max Gain Input IP2, Max Gain Nominal Voltage Swing Clipping Level DC Common Mode Voltage I/Q Amplitude Imbalance I/Q Phase Imbalance DC Offset Output Driving Capability STBY to Turn-On Delay I/Q Output 1dB Compression I/Q Output IM3 PIF, 1 = -25.5dBm, 280MHz PIF, 2 = -25.5dBm, 280.1MHz (Note 7) (Note 8) (Note 8) (Notes 6, 8) Single Ended, CLOAD 10pF 2 Demodulator I/Q Output (Note 6) (Note 6) 0.8 1.25 VCC - 1.19 0.2 0.6 28 1.5 0.3 -11.5 - 50 0.5 3 VP-P VP-P V dB Deg mV k s dBm dBc RSOURCE = 200 Differential IF+, IF- to GND, EN = V VCTRL = 1.7V VCTRL = 0.2V VCTRL = 1.7V PIF = -22.5dBm (Note 7) PIF = -75dBm (Note 7) VCTRL = 1.7V 54 IF+, IF- to GND, EN = GND
CC
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
VCTRL
VCC
MIN
TYP 40 to 500 -79 to -22 100//1.2pF 1pF 6.8 0.9 59 -0.5 -49 -8
MAX
UNITS MHz dBm
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dB dB dB dBm dBm dBm
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LT5506
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Gain Slope Linearity Error Temperature Gain Shift Gain Control Response Time Gain Control Voltage Range Gain Control Slope Gain Control Input Impedance Delay Shift Over Gain Control Baseband Lowpass Filter -3dB Cutoff Frequency Group Delay Ripple 2xLO Input f2xLO P2xLO Frequency Range Input Power Input Power Input Impedance DC Common Mode Voltage IF Detector IF Detector Range Output Voltage Range Detector Response Time Power Supply VCC ICC IOFF ISTBY Mode Enable Disable Standby No Standby Enable Pin Voltage Enable Pin Voltage Standby Pin Voltage Standby Pin Voltage EN = High EN = Low STBY = High STBY = Low 1 0.5 1 0.5 V V V V Supply Voltage Supply Current Shutdown Current Standby Current EN = High, STBY = Low or High EN, STBY < 350mV EN = Low; STBY = High 1.8 26.5 0.2 3.6 5.25 36 30 5.5 V mA A mA Referred to IF Input For PIF = -30dBm to 8dBm With External 1.8pF Load, Settling within 10% of Final Value -30 to 8 0.3 to 1.2 100 dBm V ns 1:2 Transformer with 240 Shunt Resistor (Note 5) LC Balun (Note 5) Differential Between 2xLO+ and 2xLO- -20 80 to 1000 -5 -10 800//0.4pF VCC - 0.4 V MHz dBm dBm 7.2 8.8 5 10.4 MHz ns To Internal 0.2V Measured Over 10dB Step Variable Gain Amplifier (VGA) VCTRL = 0V to 1.4V T = -40C to 85C, VCTRL = 0V to 1.4V Settled within 10% of Final Value 0.5 0.3 100 0 to 1.7 43 25 2 dB dB ns V dB/V k ps/dB
VCC = 3V. f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the -40C to 85C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the configuration of Figure 6. The IF input transformer loss is substracted from the measured values. Note 4: Power gain is defined here as the I (or Q) output power into a 4k differential load, divided by the IF input power in dB. To calculate the voltage gain between the differential I output (or Q output) and the IF input, including ideal matching network, 10 * log(4k/50) = 19dB has to be added to this power gain.
Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2 transformer with 240 shunt resistor, 2xLO input power can be reduced to -10dBm, without degrading the phase imbalance. See Figure 11 and Figure 6. Note 6: Differential between IOUT+ and IOUT- (or differential between QOUT+ and QOUT-). Note 7: The gain control voltage VCTRL is set in such a way that the differential output voltage between IOUT+ and IOUT- (or differential between QOUT+ and QOUT-) is 800mVP-P, with the given input power PIF. Note 8: The typical parameter is defined as the mean of the absolute values of the data distribution.
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VCC = 3V. f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Gain and Noise Figure Supply Current vs Supply Voltage vs Control Voltage at 3V Supply
32 30 85C
TYPICAL PERFOR A CE CHARACTERISTICS
SUPPLY CURRENT (mA)
28 26 24 22
G, NF (dB)
25C
-40C
20 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V)
5506 G01
Gain and Noise Figure vs Control Voltage at 1.8V Supply
60 50 40 G, NF (dB) 30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
5506 G03
GAIN DEVIATIN FROM LINEAR FIT (dB)
Gain and Noise Figure vs Control Voltage and VCC
60 50 40
G, NF (dB)
30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
5506 G05
G, NF (dB)
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1.2 1.2
60 50 40 30 20 NF 10 GAIN 0 -10 0 0.3 0.6 0.9 VCTRL (V)
5506 G02
fIF = 284MHz f2xLO = 570MHz 1.2 1.5 1.8
GAIN AT 25C NF AT 25C GAIN AT -40C NF AT -40C GAIN AT 85C NF AT 85C
Gain Flatness vs Control Voltage at 1.8V Supply
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.3 0.9 0.6 VCTRL (V) 1.2 1.5
5506 G04
25C 85C
fIF = 284MHz f2xLO = 570MHz 1.5 1.8
GAIN AT -40C NF AT -40C GAIN AT 25C NF AT 25C GAIN AT 85C NF AT 85C
-40C
Gain and Noise Figure vs IF Frequency
60 GAIN, VCTRL = 1.6V 50 NF, VCTRL = 0.2V 40 GAIN, VCTRL = 0.9V 30 20 10 0 -10 10 100 IF FREQUENCY (MHz) 1000
5506 G06
NF, VCTRL = 0.9V NF, VCTRL = 1.6V
fIF = 284MHz f2xLO = 570MHz 1.5 1.8
GAIN AT 1.8V NF AT 1.8V GAIN AT 3V NF AT 3V GAIN AT 5.25V NF AT 5.25V
GAIN, VCTRL = 0.2V
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VCC = 3V. f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Total Harmonic Distortion vs IF Input Power at 3V Supply and 800mVP-P Differential Out
-30 -35 -40 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz -30 -35 -40
TYPICAL PERFOR A CE CHARACTERISTICS
Total Harmonic Distortion vs IF Input Power and IF Frequency
800mVP-P DIFFERENTIAL OUT 3V SUPPLY
THD (dBc)
THD (dBc)
-45 -50 -55 -60 -65 -60
-40C
-45 -50
THD (dBc)
25C -55 85C -20 -30 IF INPUT POWER EACH TONE (dBm)
5506 G07
-50
-40
Total Harmonic Distortion vs IF Input Power and Supply Voltage
-30 -35 -40
-40
800mVP-P DIFFERENTIAL OUT fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz
-50
MAGNITUDE (dB)
THD (dBc)
THD (dBc)
3V -45 1.8V -50 5.25V -55 -60 -60
-20 -30 IF INPUT POWER EACH TONE (dBm)
5506 G10
-50
-40
LPF Frequency Response vs Baseband Frequency and Supply Voltage
0
-5 MAGNITUDE (dB)
IF DET OUTPUT (V)
IF DET OUTPUT (V)
-10
3V 1.8V 5.25V
-15
-20
-25
0
10 15 20 5 BASEBAND FREQUENCY (MHz)
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25
5505 G13
Total Harmonic Distortion vs IF Input Power at 1.8V Supply and 800mVP-P Differential Out
-30 -35 -40 -45 -50 25C -55 -60 -60 85C -40C fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz
fIF = 280MHz fIF = 550MHz fIF = 40MHz
-60 -60
-20 -30 IF INPUT POWER EACH TONE (dBm)
5506 G08
-50
-40
-50 -40 -20 -30 IF INPUT POWER EACH TONE (dBm)
5506 G09
Total Harmonic Distortion vs IF Input Power at 500mVP-P Differential Out
fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz
LPF Frequency Response vs Baseband Frequency and Temperature
0
VCC = 3V -5
-45
-10
25C 85C -40C
-55 -40C -60 25C -65 -70 -45 85C
-15
-20
-40 -35 -30 -25 IF INPUT POWER EACH TONE (dBm)
-20
-25
0
10 15 20 5 BASEBAND FREQUENCY (MHz)
25
5505 G12
5506 G11
IF Detector Output Voltage vs IF Input CW Power at 3V Supply
1.4 1.2 1.0 0.8 0.6 0.4 0.2 -40 fIF = 280MHz 1.4 1.2 1.0 0.8 0.6 0.4
IF Detector Output Voltage vs IF Input CW Power at 1.8V Supply
fIF = 280MHz
-40C 25C
85C
-40C 25C
85C
-30 -20 -10 0 IF INPUT CW POWER (dBm)
10
5506 G14
0.2 -40
-30 -20 -10 0 IF INPUT CW POWER (dBm)
10
5506 G15
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VCC = 3V. f2xLO = 570MHz, P2xLO = -5dBm (Note 5), f IF = 284MHz, PIF = -30dBm, I and Q outputs 800mVP-P into 4k differential load, TA = 25C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) IF Detector Output Voltage vs IF Input CW Power and Supply Voltage
1.4 1.2 fIF = 280MHz
1.6 1.4
IF DET OUTPUT (V)
TYPICAL PERFOR A CE CHARACTERISTICS
IF DET OUTPUT (V)
3V 1.0
5.25V 1.8V
PHASE (DEG)
0.8 0.6 0.4 0.2 -40
-30 -20 -10 0 IF INPUT CW POWER (dBm)
PI FU CTIO S
GND (Pins 1, 4 and Exposed Pad): Ground. Pins 1 and 4 are connected to each other internally. The exposed pad is not connected internally to Pins 1 and 4. For chip functionality, the exposed pad and either Pin 1 or Pin 4 must be connected to ground. For best RF performance, Pin 1, Pin 4 and the exposed pad should be connected to RF ground. IF+, IF- (Pins 2, 3): Differential Inputs for the IF Signal. Each pin must be DC grounded through an external inductor or RF transformer with central ground tap. This path should have a DC resistance lower than 2 to ground. VCC (Pins 5 and 8): Power Supply. These pins should be decoupled to ground using 1000pF and 0.1F capacitors. VCTRL (Pin 6): VGA Gain Control Input. This pin controls the IF gain and its typical input voltage range is 0.2V to 1.7V. It is internally biased via a 25k resistor to 0.2V, setting a low gain if the VCTRL pin is left floating. IF DET (Pin 7): IF Detector Output. For strong IF input signals, the DC level at this pin is a function of the IF input signal level. EN (Pin 9): Enable Input. When the enable pin voltage is higher than 1V, the IC is completely turned on. When the input voltage is less than 0.5V, the IC is turned off, except the part of the circuit associated with standby mode. 2xLO-, 2xLO+ (Pins 10, 11): Differential Inputs for the 2xLO Input. The 2xLO input frequency must be twice that of the IF frequency. The internal bias voltage is VCC - 0.4V. STBY (Pin 12): Standby Input. When the STBY pin is higher than 1V, the standby mode circuit is turned on to prebias the I/Q buffers. When the STBY pin is less than 0.5V, the standby mode circuit is turned off. QOUT-, QOUT+ (Pins 13, 14): Differential Baseband Outputs of the Q Channel. Internally biased at VCC - 1.19V. IOUT-, IOUT+ (Pins 15, 16): Differential Baseband Outputs of the I Channel. Internally biased at VCC - 1.19V.
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5506 G16
IF Detector Output Voltage vs IF Input CW Power and IF Frequency
VCC = 3V 95 94 fIF = 280MHz fIF = 550MHz 1.0 0.8 0.6 0.4 0.2 -40 fIF = 40MHz 93 92 91 90 89
Phase Relation Between I and Q Outputs vs LO Input Power
fIF = 284MHz, 25C fIF = 284MHz, -40C fIF = 284MHz, 85C fIF = 40MHz, 25C fIF = 550MHz, 25C
1.2
-30
0 IF INPUT CW POWER (dBm)
-20
-10
10
5506 G17
88 -20
-15
0 -5 -10 LO INPUT POWER (dBm)
5
10
5506 G18
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IF + 2 IF - 3 VGA I-MIXER CLIPPER LPF 16 IOUT+ 15 IOUT- 7 IF DET VCTRL 2xLO + 6 11 /2 2xLO - 10 9 EN Q-MIXER LPF
+ 14 QOUT - 13 QOUT
90
0
CLIPPER 12 STBY
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APPLICATIO S I FOR ATIO
The LT5506 consists of variable gain amplifier (VGA), I/Q demodulator, quadrature LO generator, hard clipping amplifiers (clippers), lowpass filters (LPFs) and bias circuitry. The IF signal is fed to the inputs of the VGA. The VGA gain is typically set by an external signal in such a way that the amplified IF signal delivered to the I/Q mixers is constant. The IF signal is then converted into I/Q baseband signals using the I/Q down-converting mixers. The quadrature LO signals that drive the mixers are internally generated from the on-chip divide-by-two circuit. The I/Q signals are passed through a pair of hard-clipping amplifiers (clippers), which protect the subsequent lowpass filters from overloading. After externally setting the required gain, these amplifiers should not clip. However, in the event of overload, they reduce the settling time of the (optional) external AC coupling capacitors by preventing asymmetrical charging and discharging effects. The second order baseband lowpass filters remove the out-of-band noise and harmonic content generated by the mixers and the clippers. The I/Q baseband outputs are buffered by output drivers. VGA and Input Matching The VGA has a nominal 60dB gain control range with a frequency range of 40MHz to 500MHz. The inputs of the VGA must have a DC return to ground. This can be done using a transformer with a central tap (on secondary) or an LC matching circuit with a matched impedance at the frequency of interest and near zero impedance at DC. The
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differential AC input impedance of the LT5506 is about 200, thus a 1:4 (impedance ratio) RF transformer with central tap can be used. In Figure 6, the evaluation board schematic is shown using a 1:4 transformer. The measured input sensitivity of this board is about -82.6dBm for a 10dB signal-to-noise ratio. In the case of an LC matching circuit, the circuit of Figure 1 can be used. In Table 1 the values are given for a range of IF frequencies. The matching circuit of Figure 1 approaches 180 phase shift between IF+ and IF- in a broad range around its center frequency. However, some amplitude mismatch occurs if the circuit is not tuned to the center frequency. This leads to reduced circuit linearity performance, because one of the inputs carries a higher signal compared to the perfectly balanced case. A 10% frequency shift from the center frequency results in about a 2dB gain difference between the IF+ and IF- inputs. This results in a 1.5dB higher IM3 contribution from the input stage which leads to a 0.75dB drop in IIP3. Moreover, the IIP2 of the circuit is also reduced which can lead to a higher second order harmonic contribution. The circuit can be driven single ended, but this is not recommended because it leads to a 3dB drop in gain and a considerable increase in IM5 and IM7 components. The single-ended noise figure increases by 4dB if one IF input is directly grounded and increases by 1.5dB if one IF input is grounded via a 1H inductor. An IF input cannot be left open or connected via a resistor to ground because this will disturb the internal biasing, reducing the gain, noise and linearity performance. For optimal performance, it is important to keep the DC impedance to ground
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APPLICATIO S I FOR ATIO
C3 56pF IF INPUT L1 56nH TO IF
+
TO IF - L3 120nH C1 5.6pF L2 56nH C2 5.6pF L1 15nH
5506 F01
Figure 1. IF Input Matching Network at 280MHz Table 1. The Component Values of Matching Network L1, L2, L3, C1, C2 and C3.
fIF(MHz) 50 100 150 200 250 300 350 400 450 500 L1, L2(nH) 340 159 106 80 64 53 45 40 35 32 C1, C2(pF) 34 15.9 10.6 8.0 6.4 5.3 4.5 4.0 3.5 3.2 L3(nH) 1800 470 470 470 120 120 120 120 120 120 C3(pF) 820 220 220 220 56 56 56 56 56 56
of both IF inputs lower than 2. In the matching network of Figure 1, inductor L3 is used for supplying the DC bias current to the IF+ input. To keep the DC resistance of L3 below 2, 120nH is used. This disturbs the matching network slightly by causing the frequency where the S11 is minimal to be lower than the frequency where the amplitudes of IF+ and IF- are equal. To compensate for this, the value of coupling capacitor C3 is lowered and will contribute some correcting reactance. For low frequencies, it might not be possible to find any practical inductor value for L3 with DC resistance smaller than 2. In that case it is recommended to use a transformer with central tap. The tolerance for the components in Figure 1 can be 10% for a return loss higher than 16dB and a gain reduction due to mismatch less than 0.3dB. It is possible to simplify the input matching circuit and compromise the performance. In Figure 2a, the simplified matching network is given.
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IF INPUT TO IF + C1 10pF TO IF - L2 15nH 75 1mA VBIAS 1mA 75 IF + IF -
5506 F02
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(2a)
(2b)
Figure 2a. Simplified IF Input Matching Network at 280MHz and Figure 2b. Simplified Circuit Schematic of the IF Inputs
This matching network can deliver equal amplitudes to the IF + and IF - inputs for a narrow frequency region, but the phase difference between the inputs will not be exactly 180 degrees. In practice, the phase shift will be around 145 degrees, depending on the quality factor of the network. This will result in a reduction in the gain. The higher the chosen quality factor, the closer the phase difference will approach 180 degrees. However, a higher quality factor will reduce bandwidth and create more loss in the matching network. For minimum board space, 0402 components are used. The measured noise figure for maximum gain with this matching network is about 8dB, and the maximum gain about 57dB. Assuming 0402 inductors with Q = 35, the insertion loss of this network is about 2.5dB. The tolerance for the components in Figure 2a can be 10% for a return loss higher than 10dB and a gain reduction due to mismatch less than 0.5dB. The measured input sensitivity for this matching network (see also Figure 11) is about -82.7dBm for a 10dB signal-to-noise ratio. The gain of the VGA is set by the voltage at the VCTRL pin. For high gain settings, both the noise figure and the input IP3 will be low. From a noise figure point of view, it is advantageous to work as closely as possible to the maximum gain point. However, if the voltage at the VCTRL pin is increased beyond the maximum gain point (where additional increase in control voltage does not give an increase in gain), the response time of the gain control circuit is increased. If control speed is crucial, a few dB of gain margin should be allowed from the highest gain point to be sure that at all temperatures, the maximum gain setting is not crossed. At low gain settings, the noise figure and the input IP3 will be high. Optionally, the control
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APPLICATIO S I FOR ATIO
voltage VCTRL can be set lower than 0.2V. The normal range is from VCTRL = 0.2V to 1.7V, which results in a nominal gain range from 0.9dB to 59dB. The linear-in-dB gain relation with the VCTRL voltage still holds for control voltages as low as -0.4 V. This results in an extended gain control range of -19.7dB to 59dB. The VCTRL pin is a very sensitive input because of its high input impedance and therefore should be well shielded. Signal pickup on the VCTRL pin can lead to spurs and increased noise floor in the I/Q baseband outputs. It can degrade the linearity performance and it can cause asymmetry in the two-tone test. If control speed is not important, 1F bypass capacitors are recommended between VCTRL and ground. A fast responding peak detector is connected to the VGA input, sensitive to signal levels above the signal levels where the VGA is operating in the linear range. It is active from -22dBm up to 5dBm IF input signal levels. The DC output voltage of this detector (IF DET) can be used by the baseband controller to quickly determine the presence of a strong input level at the desired channel, and adjust gain accordingly. Figure 3a shows the simplified circuit schematic of the IF DET output. I/Q Demodulators The quadrature demodulators are double balanced mixers, down-converting the amplified IF signal from the VGA into I/Q baseband signals. The quadrature LO signals are generated internally from a double frequency external CW signal. The nominal output voltage of the differential I/Q baseband signals should be set to 0.8VP-P or lower, depending on the linearity requirements. The magnitudes of I and Q are well matched and their phases are 90 apart. Quadrature LO Generator The quadrature LO generator consists of a divide-by-two circuit and LO buffers. An input signal (2xLO) with twice the desired IF signal frequency is used as the clock for the divide-by-two circuit, producing the quadrature LO signals for the demodulators. The outputs are buffered and then drive the down-converting mixers. With a fully differential approach, the quadrature LO signals are well matched. Second harmonic content (or higher order even harmonics) in the external 2xLO signal can degrade the 90 phase shift between I and Q. Therefore, such content should be
2xLO INPUT
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VCC VCC + 400mV - 8k 8k 2xLO + 2xLO - IF DET 1k 3.8k
5506 F03
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(3b)
Figure 3a. Simplified Circuit Schematic of the IF DET Output and Figure 3b. The 2xLO Inputs
3.3pF TO 2xLO+ 39nH TO 2xLO- 3.3pF TO 2xLO-
5506 F04
100pF 2xLO INPUT 2xLO INPUT 1:4 56 TO 2xLO+ 240 TO 2xLO- 100pF TO 2xLO+
(4a)
(4b)
(4c)
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band Tuned to 570MHz, 4b) Wide Band, 4c) Single-Ended Wide Band
minimized. Figure 3b shows the simplified circuit schematic of the 2xLO inputs. Depending on the application, different 2xLO input matching networks can be chosen. In Figure 4, three examples are given. The first network provides the best 2xLO input sensitivity because it can boost up the 2xLO differential input signal using a narrow-band resonant approach. The second network gives a wide-band match, but the 2xLO input sensitivity is about 2dB lower. The third network gives a simple and less expensive wideband match, but 2xLO input sensitivity drops by about 9dB. The IF input sensitivity doesn't change significantly using either of the three 2xLO matching networks. Baseband Circuit The baseband circuit consists of I/Q hard limiters (clippers), I/Q lowpass filters and I/Q output buffers. The hard limiter operates as a linear amplifier normally. However, if a high level input temporarily overloads the linear amplifier, then the circuit will limit symmetrically, which will help to prevent the filter and output buffer from overloading. This speeds up recovery from an overload event,
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LT5506
APPLICATIO S I FOR ATIO
which can occur during the gain settling. It also helps to reduce the high frequency spectral content at the I/Q outputs during overload. The second order integrated lowpass filters are used for filtering the down-converted baseband signals for both the I channel and the Q channel. They serve as antialiasing and pulse-shaping filters. The I/Q filters are well matched in gain response and group delay. The 3dB corner frequency is typically 8.8MHz with a group delay ripple of 5ns. The I/Q outputs can drive 2k in parallel with a maximum capacitive loading of 10pF, from all four pins to ground. The outputs are internally biased at VCC - 1.19V. Figure 5 shows the simplified output circuit schematic of the I channel or Q channel. The I/Q baseband outputs can be DC-coupled to the inputs of a baseband chip. For AC-coupled applications with large capacitors, the STBY pin can be used to pre-bias the outputs to nominal VCC - 1.19V at much reduced current. This mode draws only 3.6mA supply current. When the EN pin is then driven high (>1V), the chip is quickly switched to normal operating mode, avoiding the introduction of large charging time constants. Table 2 shows the logic of
VCC3 C37 0.1F R50 2k R45 1k R46 3.09k R49 2k C32 2.2pF 16 T1, 1:4,TR-R JTX-4-10T MINI-CIRCUITS 1 6 15 14 13 IOUT+ IOUT- QOUT+ QOUT- J3 IFIN C43 22nF 1 2 3 4 GND IF
+
C35 4.7F C34 0.1F
J1 IOUT
R47 49.9
C31 1F 6
7
+ -
3
U3 LT1809CS 4
2
C33 0.1F
R48 3.09k
IF - GND
VCC1 C22 1F VCTRL R51 100 C25 1.5pF C16 1nF C15 1nF C39 1F
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
sn5506 5506fs
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Table 2. The Logic of Different Operating Modes
EN Low Low High STBY Low High Low or High Comments Shutdown Mode Standby Mode Normal Operation Mode
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the EN pin and STBY pin. In both normal operating mode and standby mode, the maximum discharging current is about 300A, and the maximum charging current is more than 4mA. In Figure 5 the simplified circuit schematic of the STBY (or EN) input is shown.
VCC VCC
I CHANNEL (OR Q CHANNEL): DIFFERENTIAL SIGNALS FROM LPF
IOUT+ (OR QOUT+) IOUT- (OR QOUT-) STBY (OR EN) 300A 300A
22k
5506 F05
Figure 5. Simplified Circuit Schematic of I Channel (or Q Channel) Outputs and STBY (or EN) Input
IOUT+ IOUT- QOUT+ QOUT- C36 4.7F C27 0.1F R41 1k R39 3.09k C28 0.1F R42 2k C29 2.2pF C38 0.1F
R43 2k
3
+ -
7 6
C30 1F
2
U2 LT1809CS 4
R44 49.9
J2 QOUT
R40 3.09k R35 VCC2 20k
STBY U1 LT5506
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T2, 1:4, TR-R C45 22nF JTX-4-10T MINI-CIRCUITS R52 240 6 1
J4 2XLO
11 2XLO+ 10 2XLO - EN 9
R36 20k IF VCC VCTRL DET VCC 5 6 7 8 0 GND 1 = EN 2 = STBY
5506 F04 SW1 OVERLOAD C26 NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED 1.8pF COMPONENTS ARE INCLUDED FOR MEASUREMENT PURPOSES ONLY. BOARD NUMBER: DC468A (NARROW-BAND VERSION: DC535A) C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
LT5506
APPLICATIO S I FOR ATIO
Figure 7. Component Side Silkscreen of Evaluation Board
Figure 9. Bottom Side Silkscreen of Evaluation Board
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Figure 8. Component Side Layout of Evaluation Board Figure 10. Bottom Side Layout of Evaluation Board
sn5506 5506fs
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LT5506
APPLICATIO S I FOR ATIO
15nH RX INPUT: 2.4GHz TO 2.5GHz 1.8V 1F 2 VGA 15nH 3 0 7 6 Q-MIXER 90 f/2 12 LT5506 3.3pF 0,1,4 9 STBY EN
5506 F11
10pF 280MHz IF SAW BP FILTER
RX FRONT END 1ST LO, 2.12GHz TO 2.22GHz MAIN SYNTHESIZER 2ND LO, 560MHz -10dBm 3.3pF
AUX SYNTHESIZER
11 39nH 10
Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
PACKAGE DESCRIPTIO
UF Package 16-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1692)
4.00 0.10 (4 SIDES) 0.72 0.05 PIN 1 TOP MARK 1 4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES) 2.15 0.10 (4-SIDES) 2 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 0.55 0.20 15 16
PACKAGE OUTLINE 0.30 0.05 0.65 BCS RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED
RELATED PARTS
PART NUMBER DESCRIPTION LT5500 LT5502 LT5503 LT5504 LTC5505 LTC5507 LT5511 LT5512 1.8GHz to 2.7GHz Receiver Front End 400MHz Quadrature IF Demodulator with RSSI 800MHz to 2.7GHz RF Measuring Receiver 100kHz to 1000MHz RF Power Detector High Signal Level Upconverting Mixer High Signal Level Downconverting Mixer COMMENTS 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dBm Limiting Gain, 90dB RSSI Range 2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated 2.7V to 6V Supply, 40dB Dynamic Range, Temperature Compensated RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer DC-3GHz, 21dBm IIP3, Integrated LO Buffer
sn5506 5506fs LT/TP 1002 2K * PRINTED IN USA
1.2GHz to 2.7GHz Direct IQ Modulator and Mixer 1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwidth RF Power Detectors with >40dB Dynamic Range 2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
www.linear.com
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1nF VCC 5, 8 HARD I-MIXER CLIPPER LPF BASEBAND PROCESSOR 16 15 I-OUTPUTS IF DET VCTRL Q-OUTPUTS A/D A/D D/A A/D 14 13 LPF HARD CLIPPER
(UF) QFN 0802
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0.30 0.05 0.65 BSC
(c) LINEAR TECHNOLOGY CORPORATION 2002

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